This invention relates to a semiconductor integrated circuit device, and more particularly to a technique effective for use in layout design of a high speed digital processor constituted by a gate array integrated circuit using an ECL (Emitter Coupled Logic) circuit as a basic structural constituent, for example.
ECL circuit consisting of bipolar transistors are now available, as are gate array integrated circuit using such ECL circuit as their basic structural constituent. Furthermore, a high speed digital processor consisting of such a gate array integrated circuit is available.
In the high speed digital processor or the like of the kind described above, a wired-OR system is known as one of the means for reducing the number of circuit devices by simplifying the circuit construction, and DA (Design Automation) technique is known as one of the means for designing automatically and efficiently the circuit devices and wiring layout of the high speed digital processor or the like.
The DA technique is described, for example, in IEEE Proceedings of the 23rd Design Automation Conference, pp. 404-410 in the June issue for 1986.
FIG. 4 of the accompanying drawings shows an example of the arrangement of a high speed digital processor consisting of the gate array integrated circuit described above. The gate array integrated circuit constituting the high speed digital processor includes ECL gate cells G11.about.G18 and G61.about.G68 that the arranged in matrix. Among them, the gate cells G25, G31 and G44 include open-emitter type output transistors and their output terminals are connected commonly to form wired-OR. The output signals of these gate cells are supplied to the input terminals of the gate cells G13, G52 and G58.
When the layout of the high speed digital processor such as described above is made automatically by the DA technique, grouping and improvement in the arrangement are carried out so that the gate cells G25, G31 and G44 on the output side are arranged relatively close to one another, and a terminal resistor RE is disposed at the gate cell G44 disposed substantially at the center to form wired-OR. In this manner the wiring distance from the gate cells G25 and G31 to the terminal resistor RE is reduced and the level drop of the output signal due to the distributed resistance of these combined wiring is restricted within a predetermined range.
However, as the scale of the integrated circuit and the size of a substrate have become greater and greater with the development in the miniaturization technique of the integrated circuit, the inventor of the present invention has found that the following problems develop in the layout design described above. Namely, the distribution resistance value per unit length of the combined wiring increases with miniaturization of the combined wiring and the level drop of the output signal between the gate cell G31 and a branch node nh, for example, becomes greater and invites an erroneous operation of the input gate cell G13, or the like. Therefore, the limitation to the wiring length unavoidably must be made more severe. However, there are many cases where the requirement described above cannot be satisfied because the layout zone of the devices is enlarged with the increase in the number of the devices to be mounted and in the size of the substrate, on the contrary. In such a case, manual correction must be made. Accordingly, the effects of the DA technique cannot be fully exhibited. As the limitation to wirings and the like becomes more severe, freedom of the device layout is limited, on the contrary, and efficient layout design cannot be made.